The present invention concerns a configuration (system) for data transfer with a parallel bus system which includes an address bus, a data bus, and a control bus, and several units interfacing with them.
Such a configuration is proposed in German Patent Application No. P 41 21 152.9. The units are plugged into a subrack. During an access cycle, one of the units, as a processing unit, accesses one of the other units in an address-controlled read or write mode. In a disturbance-free access, the access cycle is completed with an acknowledge signal sent to the processing unit. In automation devices, the units can be configured, for example, as central modules, input or output modules, communication processors, or interface modules. The subrack of an automation device has, on its backplate (backplane), one or more bus cards for electrically connecting the units into the slots. The central module, which processes a control program for solving an automation problem, accesses other modules through this backplate (backplane) bus in the read or write mode, which modules end the access with a "Ready" acknowledge signal if the access was successfully completed. The access time is monitored by a timer of the central module. If the timer operating time is completed without the central module having received an acknowledge signal, it aborts the attempted access. An automation device for more complex automation tasks often consists of a central unit and a plurality of expansion units connected thereto. The operating time of the timer used for monitoring the accesses to non-existing or defective units must be set to the longest access time of the automation device plus a safety margin to safely disregard erroneous responses. Therefore the time for recognizing an access error (QVZ=Acknowledge delay) by time measurement is always greater than the maximum time of an error-free access. In addition, setting the timer is a complex problem because the access times depend on several parameters. The QVZ time should not be set too long, since it determines the duration of the bus occupancy and impairs system performance.
The acknowledge process described above is suitable for a "point-to-point" link, i.e., for data transfer from one unit to another.
Acknowledgment-controlled transfer between a unit and several other addressed units is, however, not possible, since the acknowledge signal of the fastest-responding unit is dominant and masks the time that any later acknowledge signals appear. Therefore, the latest acknowledgment cannot be detected. Transfer of data to several units must be time controlled with the time base of the order of magnitude of the aforementioned QVZ time. The time required to access several units is therefore longer than the maximum required time for a point-to-point access.
The goal of the present invention is to provide a configuration for data transmission with a parallel bus system allowing time-optimized access interruption to a non-acknowledging address, as well as an acknowledge-controlled access to several units simultaneously.